Systems in a network environment communicate information in packets that encapsulate the information according to network communication protocols. Packets transmitted from one node to another node may be transmitted through one or more intervening routers that route the packets throughout the network or between networks. The router typically includes one or more network processors to process the packets. The network processor stores packets in a memory device, such as a Synchronous Dynamic Random Access Memory (SDRAM). When a packet is added to the SDRAM, an entry, referred to as a buffer descriptor, is added to a packet queue in another memory device, such as a Static Random Access Memory (SRAM), which is used to maintain information on the packets added to the SDRAM. The SRAM further maintains a queue descriptor including information on a packet queue of buffer descriptors, including a head and tail pointers and queue count of the number of buffer descriptors in the queue. The SRAM may include multiple queues for packets in the SDRAM. The queue descriptors may be stored in an on-board buffer in the SRAM memory controller
In certain implementations, the minimum access size of the SRAM is eight bytes. The queue descriptors may be cached in buffers within the SRAM memory controller, such as on-chip buffers. To enqueue a queue descriptor onto the memory controller buffers when a packet is added to the SDRAM and a corresponding buffer descriptor is added to the packet queue in the SRAM memory, two read operations (8 bytes each) and three write operations (8 bytes each) may be performed. For instance, a write of 16 bytes (or two write transactions) is performed to evict and write back a previously cached queue descriptor in the memory controller buffer. The required queue descriptor is read, which may comprise a read of 16 bytes or 2 read transactions of 8 bytes each. The queue descriptor is then written in one write transaction, e.g., 8 bytes.
In certain implementations, a dequeue operation to remove a queue descriptor from the memory controller cache when a packet is removed from the SDRAM requires five operations, three read and two write operations. For instance, a write of 16 bytes or two write transactions is performed to evict and write back a previously cached queue descriptor from the memory controller cache. The queue descriptor is then read, which may occur in a 16 byte read, or two read transactions of 8 bytes each. Then the buffer descriptor is read in one 8 byte read transaction.
Thus, enqueue and dequeue operations consume memory bandwidth to perform the necessary read and write operations to enqueue and dequeue buffer descriptors on packet queues referencing packets added and removed from the SDRAM by the network processor.